Memory Consistency and Persistency Models for Non-Volatile Memory (NVM)

1. Introduction

Every abstraction in the Linux memory subsystem up to this point in the series has rested on one quiet assumption: if power disappears, the contents of memory disappear with it. mempool_t allocations, CXL HDM-DB coherence domains, PREEMPT_RT’s carefully bounded scheduling latencies — all of that machinery exists to manage volatile state. Non-volatile memory (NVM) breaks the assumption. When DRAM-speed, byte-addressable memory survives a power cycle, “did my write make it to memory” stops being a rhetorical question and becomes a correctness property you have to engineer for, the same way you engineer for thread safety or address space isolation.

This article is about the model the kernel and CPU jointly provide for reasoning about that property — the persistency model — and how it differs from, and interacts with, the ordinary memory consistency model you already rely on for multi-threaded code. We’ll build real x86-64 code against CLFLUSHOPT, CLWB, and SFENCE, mmap a file to stand in for a persistent-memory region, and deliberately corrupt it with SIGKILL to observe what an unordered persist actually costs you.